HW-V5-ML555-G【PDF 93/108 页】BOARD EVAL FOR VIRTEX-5 ML555

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R

SelectMAP Interface

Table 4-3:

FPGA Configuration Pin Listing (1) (Continued)

Pin

Number

M15

Net Name

FPGA_DONE

Direction

O

Pin Type

DONE

Description

Active-High signal indicating configuration is

complete

AD15

AD19,

FPGA_BUSY_B

FLASH_D0 (5)

O

I

DOUT_BUSY

IO

Active-Low Busy signal

SelectMAP data bit 0 connected to Platform Flash

P15

device

AE19

FLASH_D1 (5)

I

IO

SelectMAP data bit 1 connected to Platform Flash

device

AE17

FLASH_D2 (5)

I

IO

SelectMAP data bit 2 connected to Platform Flash

device

AF16

FLASH_D3 (5)

I

IO

SelectMAP data bit 3 connected to Platform Flash

device

AD20

FLASH_D4 (5)

I

IO

SelectMAP data bit 4 connected to Platform Flash

device

AE21

FLASH_D5 (5)

I

IO

SelectMAP data bit 5 connected to Platform Flash

device

AE16

FLASH_D6 (5)

I

IO

SelectMAP data bit 6 connected to Platform Flash

device

AF15

FLASH_D7 (5)

I

IO

SelectMAP data bit 7 connected to Platform Flash

device

L11

FORCE (2,3,4)

I

IO

Input connected from Pin 31 of Platform Flash

device

L10

C13

B13

B12

A13

H9

WIDE (2,3,4)

PCIW_EN (2,3,4)

RTR (2,3,4)

CPLD_SPARE1 (2,4)

CPLD_SPARE2 (2,4)

CPLD_SPARE3 (2,4)

I

O

O

I/O

I/O

I/O

IO

IO

IO

IO

IO

IO

Input connected from Pin 29 of CPLD

Output connected to Pin 33 of CPLD

Output connected to Pin 32 of CPLD

Spare I/O connected to CPLD pin 21

Spare I/O connected to CPLD pin 22

Spare I/O connected to CPLD pin 36

Notes:

1. Configuration signals are connected to FPGA bank 0. The reference voltage, V CCO , for this bank is 2.5V. See the ML555 board

schematics on the CD-ROM for additional information.

2. These signals are connected to FPGA bank 20. The FPGA reference voltage, V CCO , for this bank is 2.5V. See the ML555 board

schematics on the CD-ROM for additional information.

3. The Net Names and Directions for pins L11, L10, C13, and B13 were chosen to support a specific PCI/PCI-X design as described in

“CPLD Programming Examples.” The user can use these pins as spare, bidirectional pins.

4. Use LVCMOS_25 I/O standard for general-purpose I/O connected to the CPLD.

5. The Platform Flash data bus is connected to FPGA Bank 2. The FPGA reference voltage, V CCO , for this bank is 2.5V. Platform Flash

data bit 0 is also connected to FPGA bank 0 to support the Serial SelectMAP configuration.

Virtex-5 FPGA ML555 Development Kit

UG201 (v1.4) March 10, 2008

93

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